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    Ʒƫͻ룬ԸŵǾΪ䳰Ц󣬶ʵ
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2007.10.26.

й걨2007.10.31.

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ʡҵιؿ˹ڻϻƬµۣ3

Yush

ͼİhttp://www.xys-reader.org/blogs/yush/?p=6299

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ŪҪԹϽѧ̬ȶȡж



ͼƬMatlab
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http://www.nanfangdaily.com.cn/southnews/jwxy/200710300521.asp
ϻƬƬϽҵ(ͼ)
20071030 04ʱ38֡Ϸҵ-Ϸб

۾Բ˵ϻ仯

Ƭлϻ۾ӰյĿԲı仯ƺػ
鱨桷רҡʡооԱʾΪҹж
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ʱϻһִϢ״̬ļƬУÿһλλ
ĳ֣ϻ۾ͻԲ

http://it.sohu.com/20071030/n252955865.shtml
۾Բ˵ϻ(ͼ)
2007103004:53
Դ-̱
Ƭлϻ۾Ӱ޹⵽ĿԲı仯ƺػ
鱨桷רҡʡооԱʾ˵һֻ
ڴ״̬ϻܵⲿı仯Ӧֱ仯δʹ
ϻе߷ŭҲδΣյĶ



http://news.bandao.cn/news_html/200710/20071030/news_20071030_496397.s
html
յƬ
2007-10-30 09:37Դ: Ϸ
»ϻƬУϻ·б仯
̱ͼ (ԴϷб )

http://news.tom.com/2007-10-27/OI27/21222086.html
пԺרңۻϻƬû(ͼ)
20071027 13ʱ53֡걨

ϻƬרƬ

ǰմӱصʦѧ͢ٴαʾ
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͢ǴǰӦʡҵ֮ƺũĻϻƬ
м7ר֮һ

͢ƽ͵رʾֻǸ˵һ֮˵Ƭ
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ϻۣڴ̬⣬
ϻۡƬ˭ֱ£ûԭ͵»Щ̬
ϻǶḶ́

http://news.huash.com/2007-10/30/content_6643431.htm
3ϻƬüǰ(ͼ)
20071030 05:47:33

200710316ʱ3959
24mmȦF4.0ٶ1/60ʹ
㵽ĵ4ŻϻƬԭͼڽ֮⣬ǰ
ϻ۲ֹ

200710316ʱ5610
41mmȦF5.0ٶ1/25
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Ƭɱߺʡҵ


http://news.cctv.com/society/20071030/108411.shtml
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CCTV-Ƶ-¼
Ƭޡ
CCTV.com 20071030 22:32


http://news.xinhuanet.com/society/2007-10/31/content_6977444.htm
пԺѧڻϻ
20071031 09:28:00 ԴϷб

죬ý屨ѾѸƬƬϽʡҵý幫
һšƬǡĿԲ¶׹⡱ƻϻ
۾Ƭ֤ϻ仯Ҳתһ

ҾõعԱҲϵƭ
пԺѧҴӸɵشҰϻ
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ףѽ˵Ĳ˵
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ӡ㲻ǻϻġ
ӡ¼1029յıǰŵ鱨浽
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ʵû̫ϣһЩӡ֮Ƭǿ֮
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http://blog.sina.com.cn/s/blog_4f100ac001000daf.html
ؿ - BLOG
Ұϻ龰ԭ 2007-10-26 17:23:38

163959ˡһŻλԵͣ΢ƫһ㣬
ʾf4.0ڽ֮⣬Ϊģ۾λķǳԣ״
ͼƬּЧʮԣûзٺۼ
ĵھţĵţϹ49ֵԵڴˣ

165610ڶʮšĿԲ¶׹⣬ϡԿֻβ
Ƭгõһšûзı䡣


http://blog.sina.com.cn/s/blog_4f100ac001000dc5.html
ؿ - BLOG
ⳡ־羡ճ 2007-10-30 05:00:44

һϻķ粨ңν㷽ҵǳʵ
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һĿѧⱻݻһ磬ȷ˸е


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ѧѧѧԺ¿гɹƪƴװ

ߣ䱾

ƴװ, ,ƴ˴֮Ҳ

ϳɳĹѧѧѧԺֲصʵ
֮DENG Qingying, ZHANG Minxuan (ѡ), JIANG Jiang (
) ƪֱ𷢱International Symposium on Parallel and 
Distributed Processing and Applications (ISPA 2007) conference 2nd 
International Workshop on Parallel and Distributed Multimedia 
Computing (ParDMCom 2007)  Lecture Notes in Computer Science:

1.	A Parallel Infrastructure on Dynamic EPIC SMT and Its 
Speculation Optimization    LNCS Vol 4742, 2007 pp.235-244 
(http://www.springerlink.com/content/f1344v5831754223/?p=6ecffa251a2e4
5debb32ef1338980002&pi=0)  (һ)
2.	Register File Management and Compiler Optimization on EDSMT    
LNCS Vol. 4743, 2007 pp. 394-403 
(http://www.springerlink.com/content/g186714062138906/?p=6ecffa251a2e4
5debb32ef1338980002&pi=1) (Ķ)

ƪÿƪƪ  ƪ֮вͬ 
ĳȳϮ֮°:

1. "The Future of Microprocessors" ('Olukotun') by Olukotun and 
Hammond, ACM Queue vol. 3, no. 7 - September 2005

(http://www.acmqueue.com/modules.php?name=Content&pa=showpage&pid=326) 
2. "Intel Itanium Architecture Software Developer's Manual, Volume 
1:
Application Architecture Revision 2.2 January 2006" ('Intel') by 
Intel (http://download.intel.com/design/Itanium/manuals/24531705.pdf)
3. "Optimizations for the Intel Itanium Architecture Register 
Stack" ('Settle'), by Settle, Connors, Hoflehner, and Lavery. 
Proceedings of the 1st Conference on Code Generation and Optimization. 
March, 2003. 
(http://rogue.colorado.edu/draco/papers/cgo-03-register.pdf)
4. "Tuning Compiler Optimizations for Simultaneous Multithreading" 
('Loһ'), by Lo, Eggers, Levy, Parekh, and Tullsen, Proceedings of 
the 30th Annual International Symposium on Microarchitecture, December 
1997, pp 114-124 
(http://www.cs.washington.edu/research/smt/papers/smtcompiler.pdf) (
һΪοRef 7)
5. "Software-Directed Register Deallocation for Simultaneous 
Multithreaded Processors" ('LoĶ') by Lo, Parekh, Eggers, Levy, and 
Tullsen, University of Washington Technical Report #UW-CSE-97-12-01,
(http://www.cs.washington.edu/research/smt/papers/register.TR.ps), 
޶IEEE Transactions on Parallel and Distributed Systems, 
Volume 10, Issue 9 (September 1999)
6. "OpenUH: An Optimizing, Portable OpenMP Compiler" by Liao, 
Hernandez,
Chapman, Chen, and Zheng, (www2.cs.uh.edu/~copper/openuh.pdf) (
һΪοRef 9)
6. "OpenUH Compiler Suite  User's Guide" 
(http://www2.cs.uh.edu/~openuh/OpenUHUserGuide.pdf)

Ϯʰ, Ծ:

1.	һ1 : 

The combination of limited instruction parallelism suitable for 
superscalar issue, practical limits to pipelining, and a power 
ceiling limited by practical cooling limitations has limited future 
speed increases within conventional processor cores to the basic Moore
s law improvement rate of the underlying transistors.
Processor designers must find new ways to effectively utilize the 
increasing transistor budgets in high-end silicon chips to improve 
performance in ways to minimize both additional power usage and design 
complexity. And it is also useful to examine the problem from the 
point of view of different performance requirements.

Olukotun :

The combination of limited instruction parallelism suitable for 
superscalar issue, practical limits to pipelining, and a power ceiling 
limited by practical cooling limitations has limited future speed 
increases within conventional processor cores to the basic Moores 
law improvement rate of the underlying transistors.
...
Processor designers must find new ways to effectively utilize the 
increasing transistor budgets in high-end silicon chips to improve 
performance in ways to minimize both additional power usage and design 
complexity. ... so it is useful to examine the problem from the point 
of view of these different performance requirements..

2.	һ2.2:  

Explicitly Parallel Instruction Computing (EPIC) architectures 
developed by HP and Intel allow the compiler to express program 
instruction level parallelism directly to the hardware to deal with 
increasing memory latencies and penalties. Specifically, the Itanium 
architecture deploys a number of EPIC techniques which enable the 
compiler to represent control speculation, data dependence speculation, 
and predication to enhance performance. These techniques have 
individually been shown to be very effective in dealing with memory 
penalties. In addition to these techniques, the Itanium architecture 
provides a virtual register stack to reduce the penalty of memory 
accesses associated with procedure calls and to leverage the 
performance advantages of a large register file.

Settle ĵ1:

Explicitly Parallel Instruction Computing (EPIC) architectures 
allow the compiler to express program instruction level parallelism 
directly to the hardware to deal with increasing memory latencies and 
penalties. Specifically, the Itanium architecture deploys a number of 
EPIC techniques which enable the compiler to represent control 
speculation, data dependence speculation, and predication [3] to 
enhance performance. These techniques have individually been shown to 
be very effective [2] in dealing with memory penalties. In addition to 
these techniques, the Itanium architecture provides a virtual register 
stack to reduce the penalty of memory accesses associated with 
procedure calls and to leverage the performance advantages of a large 
register file.

3.	һ4:  

Todays optimizing compilers rely on aggressive code scheduling 
to hide instruction latencies. In global scheduling techniques, such 
as trace scheduling or hyperblock scheduling, instructions from a 
predicted branch path may be moved above a conditional branch, so that 
their execution becomes speculative. If at runtime, the other branch 
path is taken, then the speculative instructions are useless and 
potentially waste processor resources.
On in-order superscalars or VLIW machines, software speculation is 
necessary, because the hardware provides no scheduling assistance. On 
an EDSMT processor, multithreading is also used to hide latencies. (As 
the number of SMT threads is increased, instruction throughput also 
increases.) Therefore, the latency-hiding benefits of software 
speculative execution may be needed less, or even be unnecessary, and 
the additional instruction overhead introduced by incorrect 
speculations may degrade performance.
Our experiments were designed to evaluate the appropriateness of 
software speculative execution ... The results highlight two factors 
that determine its effectiveness for EDSMT: static branch prediction 
accuracy and instruction throughput.
Correctly-speculated instructions have no instruction overhead; 
incorrectly-speculated instructions, however, add to the dynamic 
instruction count. Therefore, speculative execution is more beneficial 
for applications that have high speculation accuracy, e.g., loop-based 
programs with either profile-driven or state-of-the-art static branch 
prediction. 
Fig. 6 compares the dynamic instruction counts between 
(profile-driven)
speculative and non-speculative versions of our applications. 
Small increases in the dynamic instruction count indicate that the 
compiler has been able to accurately predict which paths will be 
executed. Consequently, speculation may incur no penalties. Higher 
increases in dynamic instruction count, on the other hand, mean 
wrong-path speculations, and a probable loss in SMT performance. 
While instruction overhead influences the effectiveness of 
speculation, it is not the only factor. The level of instruction 
throughput in programs without speculation is also important, because 
it determines how easily speculative overhead can be absorbed. With 
sufficient instruction issue bandwidth (low IPC), incorrect 
speculations may cause no harm; with higher per-thread ILP or more 
threads, software speculation should be less profitable, because 
incorrectly-speculated instructions are more likely to compete with 
useful instructions for processor resources (in particular, fetch 
bandwidth and functional unit issue). Figure 7 contains the 
instruction throughput for each of the applications. For some programs 
IPC is higher with software speculation, indicating some degree of 
absorption of the speculation overhead. In others, it is lower, 
because of additional hardware resource conflicts, most notably L1 
cache misses.
Speculative instruction overhead (related to static branch 
prediction accuracy) and instruction throughput together explain the 
speedups illustrated in Fig. 8. When both factors were high (bizp2), 
speedups without software speculation were greatest. If one factor was 
low or only moderate, speedups were minimal or nonexistent (perlbmk 
had only speculation overhead). Without either factor (vortex), 
software speculation helped performance, and for the same reasons it 
benefits other architectures -- it hid latencies and executed the 
speculative instructions in otherwise idle functional units. For these 
applications (and a few others as well), as more threads are used, the 
advantage of turning off speculation generally becomes even larger. 
Additional threads provide more parallelism, and therefore, 
speculative instructions are more likely to compete with useful 
instructions for processor resources.
The bottom line is that, while loop-based applications should be 
compiled with software speculative execution, non-loop applications 
should be compiled without it. Doing so either improves EDSMT
program performance or maintains its current level -- performance 
is never hurt.

Lo һ6:

Todays optimizing compilers rely on aggressive code scheduling 
to hide instruction latencies. In global scheduling techniques, such 
as trace scheduling [22] or hyperblock scheduling [23], instructions 
from a predicted branch path may be moved above a conditional branch, 
so that their execution becomes speculative. If at runtime, the other 
branch path is taken, then the speculative instructions are useless 
and potentially waste processor resources.
On in-order superscalars or VLIW machines, software speculation is 
necessary, because the hardware provides no scheduling assistance. On 
an SMT processor (whose execution core is an out-of-order superscalar), 
not only are instructions dynamically scheduled and speculatively 
executed by the hardware, but multithreading is also used to hide 
latencies. (As the number of SMT threads is increased, instruction 
throughput also increases.) Therefore, the latency-hiding benefits of 
software speculative execution may be needed less, or even be 
unnecessary, and the additional instruction overhead introduced by 
incorrect speculations may degrade performance.
Our experiments were designed to evaluate the appropriateness of 
software speculative execution for an SMT processor. The results 
highlight two factors that determine its effectiveness for SMT: static 
branch prediction accuracy and instruction throughput.
Correctly-speculated instructions have no instruction overhead; 
incorrectly-speculated instructions, however, add to the dynamic 
instruction count. Therefore, speculative execution is more beneficial 
for applications that have high speculation accuracy, e.g., loop-based 
programs with either profile-driven or state-of-the-art static branch 
prediction. 
Table 5 compares the dynamic instruction counts between 
(profile-driven)
speculative and non-speculative versions of our applications. 
Small increases in the dynamic instruction count indicate that the 
compiler (with the assistance of profiling information) has been able 
to accurately predict which paths will be executed. Consequently, 
speculation may incur no penalties. Higher increases in dynamic 
instruction count, on the other hand, mean wrong-path speculations, 
and a probable loss in SMT performance. 
While instruction overhead influences the effectiveness of 
speculation, it is not the only factor. The level of instruction 
throughput in programs without speculation is also important, because 
it determines how easily speculative overhead can be absorbed. With 
sufficient instruction issue bandwidth (low IPC), incorrect 
speculations may cause no harm; with higher per-thread ILP or more 
threads, software speculation should be less profitable, because 
incorrectly-speculated instructions are more likely to compete with 
useful instructions for processor resources (in particular, fetch 
bandwidth and functional unit issue). Table 6 contains the instruction 
throughput for each of the applications. For some programs IPC is 
higher with software speculation, indicating some degree of absorption 
of the speculation overhead. In others, it is lower, because of 
additional hardware resource conflicts, most notably L1 cache misses.
Speculative instruction overhead (related to static branch 
prediction accuracy) and instruction throughput together explain the 
speedups (or lack thereof) illustrated in Figure 4. When both factors 
were high (the non-loop-based fft, li, and LU), speedups without 
software speculation were greatest, ranging up to 22%. If one factor 
was low or only moderate, speedups were minimal or nonexistent (the 
SPECfp95 applications, radix and water-nsquared had only high IPC; go, 
m88ksim and perl had only speculation overhead). Without either factor, 
software speculation helped performance, and for the same reasons it 
benefits other architectures -- it hid latencies and executed the 
speculative instructions in otherwise idle functional units.
The bottom line is that, while loop-based applications should be 
compiled with software speculative execution, non-loop applications 
should be compiled without it. Doing so either improves SMT program 
performance or maintains its current level -- performance is never hurt.

4.	Ķ4 : 

MTRM focused on supporting the effective sharing of registers in 
an EDSMT processor, using register renaming to permit multiple threads 
to share a single global register file. In this way, one thread with 
high register pressure can benefit when other threads have low 
register demands.  Unfortunately, existing register renaming 
techniques cannot fully exploit the potential of a shared register file. 
In particular, while existing hardware is effective at allocating 
physical registers, it has only limited ability to identify register 
deallocation points; therefore hardware must free registers 
conservatively, possibly wasting registers that could be better 
utilized. 
There are two types of dead registers can be deallocated: (1) 
registers allocated to idle hardware contexts, and (2) registers in 
active contexts whose last use has already retired.
To address the second type of dead registers, those in active 
threads, we investigate two mechanisms that allow the compiler to 
communicate last-use information to the processor, so that the 
renaming hardware can deallocate registers more aggressively.  Without 
this information, the hardware must conservatively deallocate 
registers only after they are redefined.
1) Special Bit communicates last-use information to the hardware 
via dedicated instruction bits (...), with the dual benefits of 
immediately identifying last uses and requiring no instruction overhead. 
It can serve as an upper bound on performance improvements that can be 
attained with the compiler's static last-use information.
2) Special Instruction is a more realistic implementation of 
Special Bit. Rather than specifying last uses in the instruction itself, 
it uses a separate instruction to specify one or two registers to be 
freed. Our compiler generates a Free Register instruction (an unused 
opcode in the IA-64 ISA) immediately after any instruction containing 
a last register use (if the register is not also redefined by the same 
instruction). Like Special Bit, it frees registers as soon as possible, 
but with an additional cost in dynamic instruction overhead. 
Current renaming hardware provides mechanisms for register 
deallocation (i.e., returning physical registers to the Idle Physic 
Register Number Queue) and can perform many deallocations each cycle.

Lo Ķ1:

Our techniques focus on supporting the effective sharing of 
registers in an SMT processor, using register renaming to permit 
multiple threads to share a single global register file. In this way, 
one thread with high register pressure can benefit when other threads 
have low register demands.  Unfortunately, existing register renaming 
techniques cannot fully exploit the potential of a benefit when other 
threads have low register demands.  Unfortunately, existing register 
renaming techniques cannot fully exploit the potential of a shared 
register file. In particular, while existing hardware is effective at 
allocating physical registers, it has only limited ability to identify 
register deallocation points; therefore hardware must free registers 
conservatively, possibly wasting registers that could be better 
utilized.
We propose software support to expedite the deallocation of two 
types of dead registers: (1) registers allocated to idle hardware 
contexts, and (2) registers in active contexts whose last use has 
already retired.
To address the second type of dead registers, those in active 
threads, we investigate five mechanisms that allow the compiler to 
communicate last-use information to the processor, so that the 
renaming hardware can deallocate registers more aggressively.  Without 
this information, the hardware must conservatively deallocate 
registers only after they are redefined.

Lo Ķ4.2:

1. Free Register Bit communicates last-use information to the 
hardware via dedicated instruction bits, with the dual benefits of 
immediately identifying last uses and requiring no instruction overhead. 
... it can serve as an upper bound on performance improvements that 
can be attained with the compilers static last-use information.
2. Free Register is a more realistic implementation of Free 
Register Bit.
Rather than specifying last uses in the instruction itself, it 
uses a separate instruction to specify one or two registers to be freed. 
Our compiler generates a Free Register instruction (an unused opcode 
in the Alpha ISA) immediately after any instruction containing a last 
register use (if the register is not also redefined by the same 
instruction). Like Free Register Bit, it frees registers as soon as 
possible, but with an additional cost in dynamic instruction overhead.
...
Current renaming hardware provides mechanisms for register 
deallocation (i.e., returning physical registers to the free register 
list) and can perform many deallocations each cycle.

5.	Ķ6 : 

The two register deallocation schemes are compared in Fig. 6 and 
Fig. 7, which charts their speedup versus no explicit register 
deallocation under different thread configurations. The Special Bit 
bars show that register deallocation can (potentially) improve 
performance significantly for small register files (80% on average, 
but ranging as high as 120%). The Special Bit results highlight the 
most attractive outcome of register deallocation: by improving 
register utilization, an EDSMT processor with small register files can 
achieve large register file performance. With multiple register 
contexts, an EDSMT processor need not double its architectural 
registers if they are effectively shared. Our results show that an 
4-context EDSMT with the effective RSE and compiler assistant can 
alleviate physical register pressure.
Special Bit is more effective at reducing the number of dead 
registers, because it deallocates them more promptly, at their last 
uses. When registers are a severe bottleneck with small register files, 
Special Instruction has a bottleneck with small register files, 
Special Instruction has a good result; while instruction overhead will 
cause a low performance with larger register files and applications 
with low register usage.

Lo Ķ4.2: 

The five register deallocation schemes are compared in Figure 6, 
which charts their speedup versus no explicit register deallocation. 
The Free Register Bit bars show that register deallocation can 
(potentially) improve performance significantly for small register 
files (77% on average, but ranging as high as 195%). The Free Register 
Bit results highlight the most attractive outcome of register 
deallocation: by improving register utilization, an SMT processor with 
small register files can achieve large register file performance, as 
shown in Figure 7. ... With multiple register contexts, an SMT 
processor need not double its architectural registers if they are 
effectively shared.
Our results show that an 8-context SMT with an FSR register file ... 
needs only 96 additional registers to alleviate physical register 
pressure ... Free Register is more effective at reducing the number of 
dead registers, because it deallocates them more promptly, at their 
last uses. When registers are a severe bottleneck, as in ... with 
small register files, Free Register  outperforms Free Register Mask. 
Free Register Mask, on the other hand, incurs less instruction overhead; 
therefore it is preferable with larger register files and applications 
with low register usage.

до863ƻ͹ȻѧѪǮȻ
ЩѧЩо Ǯ!

(XYS20071031)

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̶

      

һ  ˵

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Դӷ΢ȫ΢޲¶อĹϵף
Ļϸڣõࡣ˽죬Ѿ˶ۣ
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˵һ˥΢ɻؾɵˣһ磬
С˥˵ԻˣԻѧϰˣʹѧ˲
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ءʹʵʵѧʣۣ٣ְ
ôܲżأ

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ӡ顢ϪͬԫϹ˵װӣȫǽ
ҽĸݡֻѡءʲôأ˵ٵǵ׶
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ܿʵգƽϲµģûȷʵ飬ûй֤ݣ
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ġ߳Ǹ֤ԵʵǷǷϣɽ
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ݡҽЩʲôأǧûгѧûн
ѧ˼ҽѧ᪻ӱܣʵ֤ж̫
ˣھϲֹȵЩˣȥ˵ǡ

˵ѧһȣ־֮ʿеҪ⡣ҹ
ҽѧԶŷԴ֮᪻ˣģʷ
˽˼ص飬Ҳ˵ǻѻɡĿʶˣ
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βЧһкĵѧϰ˼
Ĺԣѵǰ־ʿ𣡶ȴҪһĨɷ
ôأ˵֪ЩԸˡʵҲҼ
ءԭ򡣹ʲôһ־񣬹ҪסǵĹ
徭ǧߵ˽죬̫ƽҲѵǾҽ
⡱ĻҪûʲôŵֻΪʷáӹ㣬ˣ
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ףӯô˵ǹⱣأǧרƾ壬ҲҢ˴
䡢ĵ̫ۡʱô˵ǹⱣأҽ
ģǶȡȡȡھȫģģǶǣʵһʣ
ſڽ࣬û۵ˡſտУ䵽ףϹ
ΪĵزԹŴҽƣӣûйļֵ
ʱЧǧԣ۾ˣҶ˵ԽԽ࣬
˵ȻжԵһƻ˾޳ɼдߺˣ
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Ϊ֤ݣԽ޲ףֱϸԴϸϲȷƷ
ȷҲͲ֪ˡ֮壬ʧ֮ǧͬҩʯɱˣ
֪˵Ķ֢ˣκ缲ҵҩ֢ҲẦ
ˡôܾôɱˣô֢ô᲻֢ҽԼҲ
ֻ֪ˣвкʹһ£Щ
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ĵҹҩӦкõģҲӦмЧģǧ
飬϶еģⲻܷ񶨣ѧ˵ۣûһڿ֤ʵġƤ
֮棬ëɸЫҧˣȥĿʶˣЩ
˼ʹ뷢ôأΪ֮ƣֻһûݵĿջ
ѧʵ·ȥýҽѧҩѧо
ǵıأܻϣϷâɣԸɡ
ҽķҹҽѧԶûй֮աʹ뱣ôأ
ôأ

ءǻƵ۵飬Ժͷ񣬴սغǸʱ顣
˵ģҲûԯѵҪ˵ȫǻƵ۵Ļ͹ˣߣ
ֵȣмۡдƪЩΪ֧ԮΪҲ
ˣջȡʤǰ˸ޣȫҪѰʵʡ

ڶ 

ͨءȫ飬Ϊ۸ݣģȫΪ
֮˵ءȫҲ޷ˡֻءֻҽѧ
ҹһѧһţȫ֮˵Ķأа˵̫ˡʮ
ܶʶ֮ʿѧ˵ԣһۣΪ˲
նۣƪֻʵ֤˵ȡʤ

ϹʱĻδŹµ˾̣ӡ
ţɮ£йףңЩȫ൱
Ȩƹܰյˡҽɮ£йҽңض
ѧĹͬ·ʡ˵֮βף
ѡְܹǣ֮ҽҩ
Ȩƪ˵ҽ̫Ԫƪ˵ΪҽΪסΪף
˵׵֡ġ׷ࡣиE֮ʬ
Բٲ֮ҩԾ֮עԻҽҲ˵ҽ
š˵ҽҲ־ҽҡ۰˵һŴ
ҽд׵ģⶼǹŴҽѧҵ֤е֧ɱɷ
֮ʿ𵤵֮ԣҽҽͲԴƷҩԣС
صıԴףȻʵۣΥ

νֻбﶯʵгأֲ
Ůۣŵѧ෴ģԽ
˼Ҳֻ˼ûԴ
ضӦΪĸͳ˲˼ӡʡӦ
ۡ˵ߣ֮Ҳ֮٣仯֮ĸɱ֮ʼ
֮Ҳβ䱾˵Ϊ죬ΪأΣ
ϣϡ˵ز˼飬ס
Ϊλã״̬մնˮ
˵ˮΪΪȶˮ˵Ŵ춯ؾ˵
˵ִ˵ѾֵһǴ˵һ¡
˵ʲô˵ۺϳɵġʲô˵ۺϳ졣
ûʲô죬ǰ˴֮һôأҲ
ģѿ¾ͳҺ壻ˮھͳ塣һأ
Ҽնˮ̸ȴ֪ԭ򡣵п
иܴ󣬵Ե嶼Ӱ졣
ܵĿڵصܵĵڿ
½ˮȿأ½Ǳȿ壬ȶ⣬
ȼաһ˵ˮģҪڿ˵ڿ
˵ˡǿأֲڵ£أ
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˵ôأУΪ³Ϊô֮࣬
ģأɴ˿֪֮˵ĸټ֮ǳ
ǳª󣬺ԣΪѧĸ

֮˵Ρ˵ӡȡУǵءˮ
硢йͷΪУ˵Ѿͬ˭ģѾû֪
ˡͿԿģûиݵ˵ֻΪûвͬ
˵ο죬е˵Ϊ˽Ȼİˡ
˴С֮˵ԭֻǰ࣬ԱץסĹؼ
ΪɣУԪءӰˮʯΪ
֮Ҳ˵ˮʯ御ֽӽ֮˵ˡ
컯ѧԽԽˣ֪ʵԪأѾаʮ֣Ҳǰ
ʮˣȻѾɰʮˣٱŹȥ˵Ŀ˵ʲôУǲˡ

֮˵ʼңīңȫ˻Ӱ졣ֻң
˵ʵܹƻҵУ񷨺ʵʵģѧɣҲ
ڲ˵Сᳫ˼ʼģӴֻǧ꣬
ǿɱѽӷ˼˵Է֪ͳȻ̲ľ
־żӲ˵ν֮СƧΥ࣬˵Լ
޽⡣Ƕֻ֮ԻȾ֮Ҳ˼֮֮֮
壿ȇȻ֪Ҳ֮ܶΪΣΪȺں
˼֮Ҳ

ףǾҽ֣ǲܾ
ִۣȴѴ̳йǽ컹ܺ˼
ᳫǵǲӱܵġ֮˵Ļģûи
ݣȴֱ䱾อɫζ֧¡ʱڡϵ丽
ᣬûû׷ԭίˡĸˣʹ֦Ҷï
Ҳֻǻ󣡲ֵۣҾͲ˵ˡ

  

ء˵ԸΡġƢΡΪأθ
󳦡СסΪʡƪƾغ͸
˼ʡرƪж塣˵νߣ(cang)
кҲʵߣأʵҲע˵
ΪˮΪʵ壬ضкʵг޻ʵˮǣ
أʵлʵ޳

ء˵˼ѾǳˡΪ
ƢЩ٣ʿʺʵʣеĻûпնҲûĶҲ
ڣΪֻ˾ûдйáض
кԽвءθСȫǻ壬еҺ壬е
壬θףȻгڣΪר𴫻йãǴƷ
Ĳֿ⣬Խие󣬷΢֪ʵĶ֪
Σ쵨֭ᡢʵĵطѪҺã
ϸĽṹе֭ϸܣӸϸܿڣѵ֭͵ҡ
ΣȡĲϣƳɵ֭͵ңҪйǲкأ
֪εҽѧãֻۼĽʽṹָܷεе֭ϸ
磬ͺ϶ضкΪΪѧδеδû
ʲôֵġ˱ž˵˵ʡô
˵ġ辫ܺǷǶֱܷ棬Ǿֻˡ

ķңܹѪҺķ
ӾѪҺӪʣעķִ
ңΣĿϣȡķ
ҽȫѭӪʺ͵ȫѪҺëϸѪ
ܣ뾲ѭϢܶʼڶм䣬ѪҺ
ƲضʵквأṹöŪˡ

ء˵ƢҲָ֪ʲôʡӦۼдۣ
˵ѪƢƺѪҺйء˵ƢѪʱҲѪ
򣩡ᣬ͵ȥӦ˵ƢѪҲǲضкġ
ƪȫƢθһ˵ʡ˵ƢΪθҺҲص
˵Ƣθߣ֮١̫˵Ƣߣθ֮Ҳ
ࡷƪ˵Ƣθûһһо١ѪƢǾ䣬Ϊ
ǻȷء˵Ƣȫ٣ƺ˵
Pankreasơ˵ȣ췢͵ʮָҲк
ǲأ֮ǽƢȣ˵ضкǴشģ

θ󳦡Сף䶨

־֡ءû׵ĽͣԡѾ
ΪΡԫΪݳΪ֬Ĥ
ôԡЩھ˼ֻΪ֬Ĥ
ǻͰ֮⡣žΪǻΧȫ壬ҵģ
ΪظҲиۺ˵
ǻǻһ˵ģҲĤĤĤĤװʲôأйʲôˣ
ͰΪ˵ߣ֮ˮɡࡷƪ
ʳʲôˮҲ̫ˡ

븮Ķ࣬˵󣬼ʹصҲܱ˵
ʡر˵ԡ衢ǡŮӰߣ֮Ҳ
ԲڵأʲضкԻ֮θ󳦡Сס
ߣ֮Ҳ죬кءԻ
֮˲ܾкҲΪʹˮȲܾ˵
ŮӰָӹǸšԡ衢ǡӹΪ࣬
θСĤĤסΪȫŴìܡ
ʵ֤ңΪܶط˵ͨҲݣͲܼԼ˵
ھţȴŲɣɲһɣ̫޴

  ظ

ء˵״λã޷ָϵ󡣵
ҽѧȴгظ״λãǴһ̸̸
˵Ļ

ʡصƪ˵ߣ֮Ҳɡߣഫ֮
٣νڳɡߣ֮٣ıǳɡߣ֮٣ϳɡ
ߣʹ֮٣ϲֳɡƢθߣ֮٣ζɡߣ֮٣
仯ɡСߣʢ֮٣ɡߣǿ֮٣ɳɡߣ
֮٣ˮɡߣݶ֮٣Һɣܳӡҹ
ҽ֪Ǵ˼ЭоԴء˵Եļ٣ࡷ
ƪ˵Ϊ֮˵躣࣬ᶯԹȡ躣㣬
תѣðĿиԡΪǾԴ
˼ЭоЩܶġָ˵ľǻۣע
˵ĵĹܣν˵ǷεĹܣı˵ǸεĹܣ˵ǵ
ܣϲ˵еĹܣ˵ĹܣŪ֧飬Ҫ˵޸
ݡʵ顢丽ᡢƲûбصˡڵо
֪תȫԵĹܡ񾭴Գֱ𵽴ȫλио
񾭴ԣԽգ۳ǻ۽˼ֳ֣
ɼţǶԺһͻֵ߿񡢳ޡ̱
ľȼǻۡ˼ǡܣָвλ򣬻ֵú
֫˶й࣬ЭСԣԡдǰԣ֪
ͨڼ˶񾭵ͨڼǰȵȡЩڶ顢
жȷ֤ݣʹЩ۶Ʋġ
˵λͣҪ٣
ʹôΪеľΪڵأΡΡ
ЩٵĹѾ˵ˡôܰνีǿ
ĹλȷνڡıǡϡЩ˵ǵĹأ
˵УʲôأƪʮصĹܣ龭ƪѪ־
ƪеʮȫûУİ硣İͬһ
ĿУָܾİ磬Ҳǽ˵ҡҺ壬
ĵ棬ûܡȴ˵ϲֹ̫Ц
˵θʹСĹܣԶΪԶ׼Բ´
ƢĹܣָǽƢȣúԶʡӦ˵
磬ľľᣬΣģĿΪ
ΪڵΪζǣΪ磬ڵΪľ
ΪڲΪΣɫΪԣΪǣΪڱ䶯ΪգΪĿ
ζΪᣬ־Ϊŭŭ˸Σʤŭ˽ʤ磬˽ʤᡣ
˵ģ˵ĴͬءȫĲظĹܱ仯
ĹϵӰ죬ıԴǻĳѨ
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֮࣬ҾͲȥˡν磬ǿġ̫
ǿͬ¶ȾͲͬȾͻͣᣬѹ
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棬̫ǿңҲȣҲȣȾͱᣬ
ԽӽĿϸԱϱ²λ
λĿϸȡԳ²ķǴϱ
ϸĿϱ½ϱ棬ֽ
Ȼϸֱַ½棬Գϲķ
ϱȥϵķ磬ܹȻתתٺܿ죬Է
ȥ׼ȷŵ򾭶ȣƫߵ˷ӭ洵һ
ɽˮ½͵صĺҲûһĹɡΪнʱ򲻻һֱ
ǰ谭ָܵӰ죬Էķùʽƶϡ
ȲǷķԴأҲǷ쳧˵ǲȷġ

ľӳɵģвģϲŻС
ģнϡЩԶľҪý飬еĿ䣬еĿеĿ
еĿƮȥϡ粻Ǹýеһ֣ô԰Ѳ
ľȫ˵أΪý飬ֻеһ֣ô
˵ȫڲľأ粻ľԭϣҲľĸĸ
ô˵ľأ

ᣬľġǿᡢᡢᣬǿᡣ
УǿֹľҲᣬֲлɷ
ǿõģǼԵλAlkaloid

⻰Ӳ⣬ĳɷֳˮʵ֮⣬Ƕ
ֻۣᡢ֮࣬Щ١Ǹɷ
ļ٣ʹЩɷ֣ҽѧϵԭҲǿġ
ôε˵ֻˣ˵ġ˵֮Ҳ⡢
֮ҲϡǬԻҲ⼸仰ǽ˵
Schneˡ̥ѧϣĲ޹ءҶģ
Ҷ̥ԼȫֿˡôȲ˵һأ
⣬̥ѧϣĲ磬ڳθ֮ģ
ĵ˵ʵߵˣ

۾ĹϵڽѧϼĺۼѧҲû
صãӲѧҽѧУҲҲĵطָβ
۾֢״ģֻлġĲΪ൨֭ѪҺ
ȫȾɫˡⲿ֢״ȫƤɻɫ
ڽĤɫǷȾɫʶԼȼ۾Ʋƣ
Ϊ׿ǻֲֻ۾ƣֶ
һƣֻƤЩطʹɫʾ
Կ۰ϱһĿĻûл죬ţ

ŭ˸Ρ˽˽Щ˵ұҽѧ
ѧԼѧƵ鱨棬ȫûлӡ֤ĵطϹ˵

˵Ϸȣ𣬻࣬ģѪѪƢ
ࡣʪʪʣƢƢ⡢ΡƢڡ
𣬽ΣƤëƤëǡ
ˮˮ̣裬ΣЩȫ
ۺʵһһ֤

˵ϷȱΪϷȱ䡣֪شԳ
ľȣľ䡣йڱ򣬳ϣ
ڱϷȱȡϰĴǣϷǡ
ǳڱϼϣϷˡ˵Ϸ𡢱˵
ͨ˵ʪΪ󣬸ֶ
ϿŴ󺣣ǹĴ½ԶϷ纬ˮ࣬纬ˮ
١ˮȥˡҪкˮ
Ķ٣پͿ죬ûо͸ˣˮͣͲ
ʹһһˮΣʹʪˡ
ˮĶ٣ѧϵʪȡʪ΢СĴˮݣ
ﵱȻҪˡʹǵĹϵΪصĶѽ
ԣʪĻֲͨˡҲ֪νָʲôأ
쿴ԲϱȷģȷԴϱ˵롣
Զ˵һҲˣأʩ˵֪֮
룬֮Խ֮Ҳ⻰˵ûȷĵط˵
ǧǰĴ󣬲ʥһˣ˭ܱأ

ĳɷ֣زͬϰʮԪȫСҪɷ֣ǰԪء
ڰѰԪصֺͰٷֱг

	Oxygenium	47.3		Silicium	27.9
	Alminium	8.2		Ferrum		4.8
	Calcium		3.7	þ	Magnesium	2.8
	Natrium		2.8		Kalium		2.5

ϱеġԭءﰴϰߣע

޻лͶɣû˵ɳʪġ
ڽɣѧʵѧѧɸɵġ
ˮ΢еԽ͵ͨġ˵н¶ܱҺ塣
¶гɣȫڴеˮˮΡķΧ
ΪҺҪúΪҺҪȣ˪ѩڻ֪
ġˮ˵ֻƬۣƣϸ˵ȶ
ˮġʪ𡢺ˮ˵ȡ

˵Ϊʳսˣζʵϣ
ǻѧòһֿζʣǻġֻһּȷ
ζҪĳɷϳءңѧӦ󶼿ɣȫ
ɣô˵רŲأ𣬴󲿷ࡣле
̿ˮȫǴӹʵеģӦ˵ľʡľȡ
ľȡ˵Ƿˡճ֪ĶҲȫǲľл
ġģʵټˮеζ󲿷Σˮ࣬
ξܽˮˮܲΡһνο
ᾧ˵Ҳȫˮˡִ֮˵ȫС
ӸģʵһվͲˣǴªģмʶǿ
ͬġ

Ѽһ죬ʿῴѾˡûпζ֪
ĵĲࡣѾɵļĸֳɷָƽļ
ûʲôͬҲζʵĺۼȴԺʣСĺѪҺ
ѪҺη֣ҲеġʹÿζʵҩҲθûв
ĵáƢĻѧɷ֣ʺ٣󲿷ǸַؼȣҲ
ε˵ϸ˵һûиݡǽ֯֯
֯ϳɵģелǵ׷أ޻ʳΡ̡ʯҡ
ᡢᡢء֮࣬ζ̵Ķ࣬ȴʵûζĶٿ
˵٣Ȼǲֿܷ˵
ǲؾ֮ʳγɷ֣ȫУѪᡢ顢ʺûв
̵ģôΪֻأ֮ġƢΡ˵
ҲСӸģֵۡ

ѪǹƢеƢʵȣѪ޹ءѪģ
ʵ飬ְ𴿴ѧĻܣûҽѧáʹӲ
еƢɽյƢҲӦø˵ѪƢѪ˵ùȥӦ˵
ѪѪƢ⣨ȼ⣬עҶҶƢ
мҶ߸ͬ˵Ƣ˵ָƢȣȫ
ϡεĲҲҶô˵أôƢ⡢֮˵
ʹˣƤëҶҶҶķȫֿ
ġôƤëƤëƢ˵ˣĲһмҶ
ҶҶûйϵô裬ε˵ִˣ

ࡢƢڡǡЩ˵Уֻзκͱͨ
ʵƢͿڵĹϵǿ͡ôأ˵Ƣࡣ
٣ܣͬһϵͳ࣬Խ
Ľ˶ԣûһϵģ

K˵ġ仪棬ѪΡ仪ë
Ƥ仪ڷڹǡΡ仪צָףע
ڽƢθСס仪ڴİףڼʮһK
ȡڵҲ˵ʮKڣԭģʮK֮ʹ
Ҳڱ֣䡪Ķ˵ĶͽѪ˵
Ҫ㣬ڱ沿ƬˡʹѪҺѪУֲ
ֻ沿KǿѪʢȫӪãͻƤ⻬ճ
Ĥ󣬶ֻ沿ֳƤë˵ǰѾ˵Ĵˡ
ǣǰҲ˵ͷҲҶϣϣû
йϵK֢״Ҳûвͷġ仪ڷ˵
ǰҲ˵ָ׵ĲҲҶָװ͸Կ
ѪɫƶѪѪϺаѪҺѭٵļƾԿһ
Щû˵йϵ촽ڲҲûйϵֻǸɫʪɿ
ƶѪҺѭӪòáѧϣ׸мģ֪
úɫģ˺Typhus abdominolisֻЩû˵Ƣ
θСסʲôϵ˵˵Ҳƪ˵ҲƢθ
С٣٣ûйܣǰ£йã
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֭ɷ֣ǸϸڵҺ壨и൨֭Lebergalle뵨ܵҷճ
ҺܳƵҵ֭BlasengalleϳɵġϵĹܣܽ֬
ΪʳθҺûʮһصĹܣûͳʮһصļ
ֵҪ˵ȫȡǸ



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Ͽһ顶ѧҽѧϵӦá

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վ㣬ջۣײٵҸоѧһЩǷǵı죬
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ڹʢУһЩռλѳý廰Ȩⲻ
ֿһѧ顶ѧҽѧϵӦá
ΪѧѧоϿ躣˽ΪȻѧίԱ
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ձɡ֮ԶҽƷϸѧ֤
߼ĽǶ֤ҽƷĿѧԻԲ߽ʾƵ;
ҿԷƳҽ䴦жǷƺͶԲ߽ʾƵ;
ӶΪҽĴ¿һ·ùʽƵķ˼ά
ķ˼άϣҽҩһ¯ʹҽ
⣬ҿԺͼϣʹ֤ι淶ִΪܣʹ
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©
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ҽҩּңҽҩּҵԭûͬ۸ĸһвͨΪʲôأ
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·ศɣȱһɡڳɱĻϵ۸ͺѱ֤
νԭ򣬶һ㣬ұԾѧģļ۸
ԶȲļ۸Ч棬ûһʩҽҩֻּг
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